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? semiconductor msm548262 1/37 ? semiconductor msm548262 262,144-word 8-bit multiport dram description the msm548262 is a 2-mbit cmos multiport dram composed of a 262,144-word by 8-bit dynamic ram, and a 512-word by 8-bit sam. its ram and sam operate independently and asynchronously. it supports three types of operations: random access to ram port, high speed serial access to sam port, and bidirectional transfer of data between any selected row in the ram port and the sam port. in addition to the conventional multiport dram operating modes, the msm548262 features block write, flash write functions on the ram port and a split data transfer capability on the sam port. the sam port requires no refresh operation because it uses static cmos flip- flops. features ? single power supply: 5 v 10% ? full ttl compatibility ? multiport organization ram : 256k word 8 bits sam : 512 word 8 bits ? fast page mode ? write per bit ? masked flash write ? masked block write ? package options: 40-pin 400 mil plastic soj (soj40-p-400-1.27) (product : msm548262-xxjs) 44/40-pin 400 mil plastic tsop (type ii) (tsopii44/40-p-400-0.80-k) (product : msm548262-xxts-k) xx indicates speed rank. product family ? ras only refresh ? cas before ras refresh ? hidden refresh ? serial read/write ? 512 tap location ? bidirectional data transfer ? split transfer ? masked write transfer ? refresh: 512 cycles/8 ms access time cycle time power dissipation ram ram operating standby sam sam 60 ns 120 ns 140 ma 8 ma 17 ns 22 ns 70 ns 140 ns 130 ma 8 ma 17 ns 22 ns 80 ns 150 ns 120 ma 8 ma 20 ns 25 ns family msm548262-60 msm548262-70 msm548262-80 e2l0016-17-y1 this version: jan. 1998 previous version: dec. 1996
? semiconductor msm548262 2/37 pin configuration (top view) pin name function a0 - a8 address input ras row address strobe cas column address strobe trg transfer/output enable we write enable pin name function sc serial clock se sam port enable dsf special function input v cc power supply (5 v) nc no connection dq1 - dq8 ram inputs/outputs sdq1 - sdq8 sam inputs/outputs qsf special function output v ss ground (0 v) sdq1 sdq2 sdq3 sdq4 trg dq1 dq2 dq3 a5 a4 v cc v ss sdq7 sdq6 sdq5 dq5 v ss dsf nc cas qsf a0 a1 a2 a3 v ss 30 29 28 27 26 25 23 22 21 24 se dq8 dq7 dq6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 34 33 32 31 38 37 36 35 v cc dq4 v ss we a6 a7 a8 ras sdq8 sc 39 40 40-pin plastic soj 1 v cc 44/40-pin plastic tsop ( ii ) (k type) 22 v cc 2 sc 3 sdq1 4 sdq2 5 sdq3 6 sdq4 7 trg 8 dq1 9 dq2 10 dq3 13 dq4 14 v ss 15 we 16 ras 17 a8 18 a7 19 a6 20 a5 21 a4 44 v ss 23 v ss 43 sdq8 42 sdq7 41 sdq6 40 sdq5 39 se 38 dq8 37 dq7 36 dq6 35 dq5 32 v ss 31 dsf 30 nc 29 cas 28 qsf 27 a0 26 a1 25 a2 24 a3 note: the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin.
? semiconductor msm548262 3/37 block diagram column address buffer row address buffer refresh counter a0 - a8 sam address buffer sam address counter sam stop control row decoder column decoder sense amp. 512 512 8 ram array gate sam gate sam sdq 1 - 8 qsf serial decoder block write control i/o control flash write control sam input buffer sam output buffer column mask register color register mask register ram input buffer ram output buffer timing generator ras cas trg we dsf sc se v cc v ss dq 1 - 8
? semiconductor msm548262 4/37 electrical characteristics absolute maximum ratings parameter symbol rating unit input output voltage v t C1.0 to 7.0 v output current i os 50 ma power dissipation p d 1w operating temperature t opr 0 to 70 c storage temperature t stg C55 to 150 c condition ta = 25c ta = 25c ta = 25c (note: 1) recommended operating conditions parameter symbol unit power supply voltage v cc v input high voltage v ih v input low voltage v il v min. 4.5 2.4 C1.0 typ. 5.0 max. 5.5 6.5 0.8 (ta = 0c to 70c) (note: 2) capacitance parameter symbol min. unit input capacitance c i pf input/output capacitance c io pf max. 8 9 output capacitance c o (qsf) pf 9 (v cc = 5 v 10%, f = 1 mhz, ta = 25c) note: this parameter is periodically sampled and is not 100% tested. dc characteristics 1 parameter symbol condition output "h" level voltage v oh i oh = C1 ma output "l" level voltage v ol i ol = 2.1 ma input leakage current i li 0 v in v cc all other pins not under test = 0 v min. 2.4 C10 max. 0.4 10 unit v m a output leakage current i lo 0 v out 5.5 v output disable C10 10
? semiconductor msm548262 5/37 dc characteristics 2 -60 -70 -80 unit note symbol item (ram) sam max. max. max. 95 85 75 ma 3, 4 i cc1 operating current standby 140 130 120 17 ( ras , cas cycling, t rc = t rc min.) active 888 standby current 60 55 50 3, 4 ( ras , cas = v ih ) 95 85 75 3, 4 ras only refresh current 140 130 120 17 ( ras cycling, cas = v ih , t rc = t rc min.) 75 70 65 3, 4 page mode current 140 130 120 18 ( ras = v il , cas cycling, t pc = t pc min.) 95 85 75 3, 4 cas before ras refresh current 140 130 120 3, 4 ( ras cycling, cas before ras , t rc = t rc min.) 95 85 75 3, 4 data transfer current 140 130 120 17 ( ras , cas cycling, t rc = t rc min.) 95 85 75 3, 4 flash write current 140 130 120 3, 4 ( ras , cas cycling, t rc = t rc min.) 95 85 75 3, 4 block write current 140 130 120 3, 4 ( ras , cas cycling, t rc = t rc min.) i cc1 a i cc2 i cc2 a i cc3 i cc3 a i cc4 i cc4 a i cc5 i cc5 a i cc6 i cc6 a i cc7 i cc7 a i cc8 i cc8 a standby active standby active standby active standby active standby active standby active standby active (v cc = 5 v 10%, ta = 0c to 70c)
? semiconductor msm548262 6/37 ac characteristics (1/3) parameter symbol note unit ns 150 140 120 ns 40 35 30 ns 25 20 15 ns 45 40 35 ns 35 3 35 3 35 3 ns 100k 80 100k 70 100k 60 t rc t prwc t aa t cac t cpa t rasp t cas t rcd max. min. max. min. max. min. -80 -70 -60 ns 90 90 85 ns 10k 25 10k 20 10k 15 14 20 20 20 ns 50 45 40 t pc t rac ns 80 70 60 10 ns 20 0 20 0 15 0 t off ns 60 60 50 ns 25 20 15 t rsh ns 80 70 60 t csh t t t rp ns 10k 80 10k 70 10k 60 t ras t rad 14 15 15 15 t asr 0 0 0 t rah 10 10 10 t asc 0 0 0 t cah 12 10 10 t ar 55 55 50 t rcs 0 0 0 t rch 11 0 0 0 t rrh 11 0 0 0 t wcs 0 0 0 t wch 15 12 10 t wcr 55 55 50 t wp 15 12 10 t rwl 20 20 15 t cwl 20 20 15 8, 14 8, 15 8, 15 8, 14 7 ns 55 50 45 ns 40 35 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 195 185 170 t rwc t ral t crp ns 40 35 30 10 10 10 t cp 10 10 10 ns ns 13 access time from column address column address hold time referenced to ras column address set-up time row address set-up time access time from cas column address hold time cas pulse width cas precharge time (fast page mode) access time from cas precharge cas to ras precharge time cas hold time write command to cas lead time output buffer turn-off delay fast page mode cycle time fast page mode read modify write cycle time row address hold time ras pulse width (fast page mode only) random read or write cycle time ras to cas delay time read command hold time read command set-up time read modify write cycle ras precharge time read command hold time referenced to ras write command to ras lead time access time from ras ras to column address delay time column address to ras lead time ras pulse width ras hold time transition time (rise and fall) write command hold time referenced to ras write command set-up time write command pulse width write command hold time ns 0 0 0 t ds ns 55 55 50 t dhr ns 15 12 10 t dh 12 12 data hold time data hold time referenced to ras data set-up time
? semiconductor msm548262 7/37 ac characteristics (2/3) parameter symbol note unit ns 45 40 35 ns 0 0 0 ns 0 0 0 ns 10 0 10 0 10 0 ns 10 10 10 t rwd t cwd t dzc t dzo t csr t ref t wsr max. min. max. min. max. min. -80 -70 -60 ns 100 90 80 ms 8 8 8 0 0 0 t awd ns 65 55 50 ns 20 20 15 t oea ns 10 10 10 ns 10 10 10 t chr ns 0 0 0 t rpc t oez t oeh ns 15 15 10 t roh t rwh 12 10 10 t fsc 0 0 0 t cfh 12 10 10 t ms 0 0 0 t mh 12 10 10 t ths 0 0 0 t thh 12 10 10 t tls 0 0 0 t tlh 12 10 10 t trp 60 60 50 t tp 20 20 20 t rsd 80 70 60 t asd 45 45 40 t csd 25 20 20 t tsl 5 5 5 13 13 ns ns ns ns ns ns ns ns ns ns 10k 10k 10k ns ns ns ns ns ns t rth 65 60 50 ns 10k 10k 10k t ath 30 25 20 ns t cth 25 20 15 ns t fsr t rfh ns 0 0 0 12 10 10 t fhr 55 55 50 ns ns 13 column address to first sc delay time column address to we delay time cas hold time for cas before ras cycle cas set-up time for cas before ras cycle cas to we delay time data to cas delay time data to trg delay time dsf set-up time referenced to ras write per bit mask data hold time write per bit mask data set-up time trg command hold time refresh period dsf hold time referenced to ras (1) ras hold time referenced to trg ras precharge to cas active time ras to we delay time we hold time access time from trg ras to first sc delay time (read transfer) trg to ras precharge time we set-up time last sc to trg lead time output buffer turn-off delay from trg dsf hold time referenced to ras (2) dsf hold time referenced to cas trg low hold time referenced to column address trg low hold time referenced to cas trg precharge time dsf set-up time referenced to cas trg high hold time trg high set-up time trg low hold time trg low set-up time trg low hold time referenced to ras cas to first sc delay time (read transfer) ns 15 15 15 t tsd ns 40 10 40 10 30 10 t sdz ns 25 25 20 t srs 10 serial output buffer turn-off delay from ras trg to first sc delay time (read transfer) last sc to ras set-up time (serial input)
? semiconductor msm548262 8/37 ac characteristics (3/3) parameter symbol note unit ns 7 5 5 ns 20 17 17 ns 5 5 5 ns 10 10 10 ns 30 25 25 t scc t scp t sca t soh t sts t tqd t cqd max. min. max. min. max. min. -80 -70 -60 ns 25 22 22 ns 25 25 25 t sc ns 7 5 5 9 ns 20 17 17 t sea ns 10 10 10 ns 30 25 25 t sth ns 25 25 25 t sqd t se t sep ns 20 0 20 0 20 0 t sez t rqd t sze 0 0 0 t szs 0 0 0 t sws 0 0 0 t swh 12 10 10 t swis 0 0 0 t swih 12 10 10 9 19 10 ns 35 35 30 ns 75 75 70 ns ns ns ns ns ns t sdd t sds ns 40 40 30 0 0 0 t sdh 12 10 10 ns ns access time from sc sc-qsf delay time sc pulse width (sc high time) sc cycle time sc precharge time (sc low time) ras to serial input delay time split transfer hold time split transfer set-up time se pulse width access time from se se precharge time serial write disable hold time serial write disable set-up time serial write enable set-up time serial input to se delay time serial input to first sc delay time serial output buffer turn-off delay from se serial output hold time from sc serial write enable hold time trg -qsf delay time cas -qsf delay time ras -qsf delay time serial input hold time serial input set-up time
? semiconductor msm548262 9/37 notes: 1. exposure beyond the "absolute maximum ratings" may cause permanent damage to the device. 2. all voltages are referenced to v ss . 3. these parameters depend on the cycle rate. 4. these parameters depend on output loading. specified values are obtained with the output open. 5. an initial pause of 200 m s is required after power up followed by any 8 ras cycles ( trg = "high") and any 8 sc cycles before proper device operation is achieved. in the case of using an internal refresh counter, a minimum of 8 cas before ras cycles instead of 8 ras cycles are required. 6. ac measurements assume t t = 5 ns. 7. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 8. ram port outputs are measured with a load equivalent to 1 ttl load and 50 pf. dout reference levels : v oh /v ol = 2.0 v/0.8 v. 9. sam port outputs are measured with a load equivalent to 1 ttl load and 30 pf. dout reference levels : v oh /v ol = 2.0 v/0.8 v. 10. t off (max.), t oez (max.), t sdz (max.) and t sez (max.) define the time at which the outputs achieve the open circuit condition, and are not referenced to output voltage levels. this parameter is sampled and not 100% tested. 11. either t rch or t rrh must be satisfied for a read cycle. 12. these parameters are referenced to cas leading edge of early write cycles, and to we leading edge in trg controlled write cycles and read modify write cycles. 13. t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the cycle is an early write cycle, and the data out pin will remain open circuit throughout the entire cycle; if t rwd 3 t rwd (min.), t cwd 3 t cwd (min.) and t awd 3 t awd (min.), the cycle is a read modify write cycle, and the data out will contain data read from the selected cell; if neither of the above sets of conditions are satisfied, the condition of the data out is indeterminate. 14. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only: if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 15. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only: if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 16. input levels at the ac testing are 3.0 v/0 v. 17. address (a0 - a8) may be changed two times or less while ras = v il . 18. address (a0 - a8) may be changed once or less while cas = v ih and ras = v il . 19. this is guaranteed by design. (t soh /t coh = t sca /t cac - output transition time) this parameter is not 100% tested.
? semiconductor msm548262 10/37 timing waveform read cycle ras cas address dsf we dq1 - 8 trg t rc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral t fsr row column t rah t asc t cah t rfh t cfh t fsc t fhr t rcs t rch t cac t rac t aa t rrh t off valid data t oea t roh t oez t thh t ths t asr "h" or "l" open
? semiconductor msm548262 11/37 fast page mode read cycle valid data ras cas address dsf we dq1 - 8 trg "h" or "l" t rasp t rp t rcd t cas t csh t crp t ar t rad t fsr row column t rah t asc t cah t rfh t cfh t fsc t fhr t rcs t rch t cac t rac t rrh t oea t oez t oea t thh t ths t asr column column t off t cp t pc t cas t cp t cas t rsh t asc t cah t cah t ral t cfh t cfh t rch t rcs t rch t rcs t cac t cac t cpa t cpa open valid data valid data t oez t aa t aa t off t asc t off t aa t oea t oez t fsc t fsc
? semiconductor msm548262 12/37 write cycle function table code rwm bwm fwm rw bw lcr a dsf 0 0 1 0 0 1 ras falling edge c we 0 0 0 1 1 1 d dq write mask write mask write mask x x x b dsf 0 1 x 0 1 1 cas falling edge e dq valid data column mask x valid data column mask color data function masked write masked block write masked flash write normal write block write load color register write mask data: "low" = mask, "high" = no mask column mask data dq1 - 4 dq1 dq2 dq3 dq4 column mask data column 0 (a0 = 0, a1 = 0) column 1 (a0 = 1, a1 = 0) column 2 (a0 = 0, a1 = 1) column 3 (a0 = 1, a1 = 1) low: mask high: no mask
? semiconductor msm548262 13/37 early write cycle ras cas address t rc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" dsf ab t rfh t fsc t cfh t fsr we c t rwh t wp t wsr dq1 - 8 de t mh t ds t dh t ms trg t thh t ths t rwl t cwl t fhr t wcr t dhr t wcs t wch
? semiconductor msm548262 14/37 late write cycle ras cas address t rc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" dsf ab t rfh t fsc t cfh t fsr we c t rwh t wp t wsr dq1 - 8 de t mh t ds t dh t ms trg t oeh t ths t rwl t cwl t fhr t wcr t dhr t rcs
? semiconductor msm548262 15/37 read modify write cycle ras cas address t rwc t ras t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" dsf ab t rfh t fsc t cfh t fsr we c t rwh t wp t wsr dq1 - 8 de t mh t ds t dh t ms trg t oeh t ths t rwl t cwl t fhr t rwd t rac t rcs t awd t dzc t oea t oez valid data t cac t thh t dzo t cwd
? semiconductor msm548262 16/37 fast page mode early write cycle t dh t ds t ds t dh t dh t ds t mh t ms ras cas address t rasp t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" dsf ab t rfh t fsc t cfh t fsr we c t rwh t wp t wsr dq1 - 8 trg t thh t ths t cwl t fhr column t asc t cah b t fsc t cfh column t asc t cah b t fsc t cfh de e e t wch t wcs t wp t wch t wcs t wp t wch t wcs t cwl t cwl t cas t cas t cp t cp t pc
? semiconductor msm548262 17/37 fast page mode read modify write cycle t mh t ms ras cas address t rasp t rp t rcd t cas t rsh t csh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" dsf ab t rfh t fsc t cfh t fsr we c t rwh t wp t wsr dq1 - 8 trg t thh t ths t cwl t fhr column t asc t cah b t fsc t cfh column t asc t cah b t fsc t cfh d in t ds t dh t awd t cas t cas t cp t cp t prwc t wp t wp t cwd t cwd t cwd t rcs t awd t cwl t cwl t awd out t cac t aa in t ds t dh out t cac t aa in t ds t dh out t cac t aa t oez t oea t oez t oea t oez t oea
? semiconductor msm548262 18/37 ras only refresh cycle ras cas address t rc t ras t rp t crp row t rah t asr "h" or "l" dsf we dq1 - 8 trg t thh t ths t rfh t fsr t rpc open
? semiconductor msm548262 19/37 cas before ras refresh cycle ras cas address t rc t ras t rp t csr "h" or "l" dsf we dq1 - 8 trg t rpc t rp t rpc t chr inhibit falling transition t off open
? semiconductor msm548262 20/37 hidden refresh cycle ras cas address t rc t ras t rp t rcd t chr t rsh t crp t ar t rad t ral row column t rah t asc t cah t asr "h" or "l" dsf t rfh t fsc t cfh t fsr we dq1 - 8 valid data trg t thh t ths t fhr t rrh t ras t rcs t off t aa t rac t cac t oez t oea open
? semiconductor msm548262 21/37 read transfer 1 ras cas address dsf we dq1 - 8 trg t rc t ras t rp t rcd t cas t rsh t csh t ar t rad t ral t fsr row sam start t rah t asc t cah t rfh t asr "h" or "l" t wsr t rwh t tp t tlh t tls t trp t asd t csd t rsd sc t sc note 2 t srs t tsd t scp t scc t sc din t sih sdq1 - 8 t sis data out t sca t szs t soh t sca qsf t tqd t cqd t rqd note 3 note 3 open note 1: se = "l" note 2: there must be no rising transitions note 3: qsf = "l"-- lower sam (0 - 255) is active qsf = "h"-- upper sam (256 - 511) is active
? semiconductor msm548262 22/37 read transfer 2 (real time read transfer) ras cas address dsf we dq1 - 8 trg t rc t ras t rp t rcd t cas t rsh t csh t ar t rad t ral t fsr row sam start t rah t asc t cah t rfh t asr "h" or "l" t wsr t rwh t tp t tls t trp t ath t cth sc t scp t sc sdq1 - 8 data out qsf t tqd note 2 note 2 t rth t scc t tsl t tsd data out data out data out t sca t soh t sca t soh open note 1: se = "l" note 2: qsf = "l"-- lower sam (0 - 255) is active qsf = "h"-- upper sam (256 - 511) is active
? semiconductor msm548262 23/37 split read transfer note 1: se = "l" note 2: qsf = "l"-- lower sam (0 - 255) is active qsf = "h"-- upper sam (256 - 511) is active note 3: si is the sam start address in before srt ras cas address dsf we dq1 - 8 trg t rc t ras t rp t rcd t cas t rsh t csh t ar t rad t ral t fsr row sam start sj t rah t asc t cah t rfh t asr "h" or "l" t wsr t rwh t tlh t tls t cth t ath t rth sc 511 (255) 254 (510) 255 (511) sj+256 (s j) t sts sdq1 - 8 qsf t sqd note 2 note 2 data out data out t soh data out t sca t sc t soh t sca data out data out data out note 2 t sqd t scp t scc open s i (si+256)
? semiconductor msm548262 24/37 masked write transfer note 1: se = "l" note 2: there must be no rising transitions note 3: qsf = "l"-- lower sam (0 - 255) is active qsf = "h"-- upper sam (256 - 511) is active ras cas address dsf we dq1 - 8 trg t rc t ras t rp t rcd t cas t rsh t csh t ar t rad t ral t fsr row sam start t rah t asc t cah t rfh t asr "h" or "l" t wsr t rwh t tlh t tls t csd t rsd sc t sc note 2 t srs t scp t scc t sc dout t sdz sdq1 - 8 t sdh t sds t sdh qsf t sdd t cqd t rqd note 3 note 3 mask data t mh t ms dout t soh data in t sds data in open
? semiconductor msm548262 25/37 masked split write transfer note 1: se = "l" note 2: qsf = "l"-- lower sam (0 - 255) is active qsf = "h"-- upper sam (256 - 511) is active note 3: si is the sam start address in before swt ras cas address dsf we dq1 - 8 trg t rc t ras t rp t rcd t cas t rsh t csh t ar t rad t ral t fsr row sam start sj t rah t asc t cah t rfh t asr "h" or "l" t wsr t rwh t tlh t tls t cth t ath t rth sc t sts sdq1 - 8 qsf t sqd note 2 note 2 data in data in t sds data in t sc t sdh note 2 t sqd t scp t scc data in data in data in t sds t sdh t ms t mh mask data open 511 (255) 254 (510) 255 (511) sj+256 (s j) s i (si+256)
? semiconductor msm548262 26/37 serial read cycle serial write cycle se sc sdq1 - 8 t sep data out data t sez t soh data out data out t scc t sea t soh t soh t sca t sc data t scp t sca t sca se sc sdq1 - 8 t sep t sc t swh t scc data in data in t sdh t sds data in data in t swih t sze t sds t sdh t scp t swis t sws "h" or "l"
? semiconductor msm548262 27/37 pin functions address input: a0 - a8 the 18 address bits decode 8 bits of the 2,097,152 locations in the msm548262 memory array. the address bits are multiplexed to 9 address input pins (a0 - a8) as standard dram. 9 row address bits are latched at the falling edge of ras . the following 9 column address bits are latched at the falling edge of cas . row address strobe: ras ras is a basic ram control signal. the ram port is in standby mode when the ras level is "high". as the standard drams ras signal function, ras is the control input that latches the row address bits, and a random access cycle begins at the falling edge of ras . in addition to the conventional ras signal function, the level of the input signals cas , trg , we and dsf at the falling edge of ras , determines the msm548262 operation mode. column address strobe: cas as the standard drams cas signal function, cas is the control input signal that latches the column address input and the state of the special function input dsf to select in conjunction with the ras control, either read/write operations or the special block write feature on the ram port when the dsf is held "low" at the falling edge of ras . cas also acts as a ram port output enable signal. data transfer/output enable: trg trg is also a control input signal having multiple functions. as the standard drams oe signal function, trg is used as an output enable control when trg is "high" at the falling edge of ras . in addition to the conventional oe signal function, a data transfer operation is started between the ram port and the sam port when trg is "low" at the falling edge of ras . write per bit/write enable: we we is a control input signal having multiple functions. as the standard drams we signal function, this is used to write data into the memory on the ram port when we is "high" at the falling edge of ras . in addition to the conventional we signal function, the we determines the write-per-bit function, when we is "low" at the falling edge of ras during ram port operations. the we also determines the direction of data transfer between the ram and sam. when the we is "high" at the falling edge of ras , the data is transferred from ram to sam (read transfer). when the we is "low" at the falling edge of ras , the data is transferred sam to ram (write transfer).
? semiconductor msm548262 28/37 write mask data/data input and output: dq1 - dq8 in conventional write-per bit mode, the dq pins function as mask data at the falling edge of ras . data is written only to high dq pins. data on low dq pins is masked and internal data is retained. after that, they function as input/output pins similar to a standard dram. serial clock: sc sc is a main serial cycle control input signal. all operations of the sam port are synchronized with the serial clock sc. data is shifted in or out of the sam registers at the rising edge of sc. in a serial read cycle, the output data becomes valid on the sdq pins after the maximum specified serial access time t sca from the rising edge of sc. in a serial write cycle, data on sdq pins at the rising edge of sc are fetched into the sam register. serial enable: se the se is a serial access enable control and serial read/write control signal. in a serial read cycle, se is used as an output control. in a serial write cycle, se is used as a write enable control. when se is "high", serial access is disabled. however, the serial address pointer location is still incremented when sc is clocked even when se is "high". special function input: dsf the dsf is latched at the falling edge of ras and cas . it allows for the selection of several ram ports and transfer operating modes. in addition to the conventional multiport dram, the special functions consisting of flash write, block write, load/read color register, and split read/write transfer can be invoked. special function output: qsf qsf is an output signal, which during split register mode indicates which half of the split sam is being accessed. qsf "low" indicates that the lower split sam (0 - 255) is being accessed. qsf "high" indicates that the upper sam (256 - 511) is being accessed. serial input/output: sdq1 - sdq8 serial input/output mode is determined by the most recent read or write transfer cycle. when a read transfer cycle is performed, the sam port is in the output mode. when a write transfer cycle is performed, the sam port is switched from output mode to input mode.
? semiconductor msm548262 29/37 operation modes table-1 shows the function truth table for a listing of all available ram ports, and transfer operation of msm548262. the ram port and data transfer operations are determined by the state of cas , trg , we and dsf at the falling edge of ras , and by the level of dsf at the falling edge of cas . table-1. function truth table ras code address cas trg we dsf dsf ras cas write mask color register 0*** **** cbr cas / we ras w/io cas function cbr refresh 11*0row* ror ras only refresh 1000*rowtapwm1* yes mwt masked write transfer 1001*rowtapwm1* yes mswt masked split write transfer 1010*rowtap* * rt read transfer 1011*rowtap* * srt split read transfer 11000row column wm1 din, dout yes rwm read/write (mask) 11001row column wm1 yes use bwm masked block write 1101*row*wm1 yes use fwm masked flash write 11100row column * din, dout no rw read/write (no mask) 11101row * no use bw block write (no mask) 11111row* * load lcr load color register a2c - 8c column a2c - 8c column select column select color data if the dsf is "high" at the falling edge of ras , special functions such as split transfer, flash write, load color register can be invoked. if the dsf is "low" at the falling edge of ras and "high" at the falling edge of cas , the block write feature can be invoked.
? semiconductor msm548262 30/37 ram port operation ram read cycle: ras falling edge --- trg = cas = "h", dsf = "l" cas falling edge --- dsf = "l" row address is entered at the falling edge of ras and column address at the falling edge of cas to the device as in conventional dram. when the we is "high" and trg is "low" while cas is "low", the data outputs through dq pins. ram write cycle: ras falling edge --- trg = cas = "h", dsf = "l" cas falling edge --- dsf = "l" 1) write cycle with no mask: ras falling edge -- we = "h" if we is set "low" at the falling edge of cas after ras goes "low" a write cycle is excuted. if we is set "low" before the cas falling edge, this cycle becomes an early write cycle, and all dq pins attain high impedance. all 8 data are latched on the falling edge of cas . if we is set "low" after the cas falling edge, this cycle becomes a late write cycle, and all 8 data are latched on the falling edge of we . 2) write cycle with mask: ras falling edge -- we = "l" if we is set "low" at the falling edge of ras , the mask write mode can be invoked. mask data is loaded and used. the mask data on dq1 - dq8 is latched into the write mask register at the falling edge of ras . when the mask data is low, writing is inhibited into the ram and the mask data is high, data is written into the ram. this mask data is in effect during the ras cycle. in page mode cycle the mask data is retained during page access.
? semiconductor msm548262 31/37 load/read color register: ras falling edge --- cas = trg = we = dsf = "h" cas falling edge --- dsf = "h" the msm548262 is provided with an on-chip 8-bit color register for use during the flash write or block write operation. each bit of the color register corresponds to one of the dram i/o blocks. the data presented on the dqi lines is subsequently latched into the color register at the falling edge of either cas or we whichever occurs later. the read color register cycle is activated by holding we "high" at the falling edge of cas , and throughout the remainder of the cycle. the data in the color register becomes valid on the dqi lines after the specified access times from ras and trg are satisfied. during the load/read color register cycle, the memory cells on the row address latched at the falling edge of ras are refreshed. flash write: ras falling edge --- cas = trg = dsf = "h", we = "l" flash write allows for the data in the color register to be written into all the memory locations of a selected row. each bit of the color register corresponds to one of the dram i/o blocks. the flash write operation can be selectively controlled on an i/o basis in the same manner as the write per bit operation. the mask data is the same as that of a ram write cycle.
? semiconductor msm548262 32/37 block write: ras falling edge --- cas = trg = "h", dsf = "l" cas falling edge --- dsf = "h" block write allows for the data in the color register to be written into 4 consecutive column address locations, starting from a selected column address in a selected row. the block write operation can be selectively controlled on an i/o basis, and a column mask capability is also available. during a block write cycle, the 2 least significant column address locations (a0c and a1c) are internally controlled, and only the 7 most significant column addresses (a2c - a8c) are latched at the falling edge of cas . 1) no mask block write: we "high" at the falling edge of ras the data on 8 dq pins is all cleared by the data of the color register. 2) masked block write: we "low" at the falling edge of ras the mask data is the same as that of a ram write cycle. sam port operation single register mode high speed serial read or write operation can be performed through the sam port independent of the ram port operation, except during read/write transfer cycles. the preceding transfer operation determines the direction of data flow through the sam port. if the preceding transfer is a read transfer, the sam port is in the output mode. if the preceding transfer is write transfer, the sam port is in the input mode. serial data can be read out of the sam after a read transfer has been performed. the data is shifted out of the sam starting at any of the 512 bits locations. the tap location corresponds to the column address selected at the falling edge of cas during the read or write transfer cycle. the sam registers are configured as a circular data register. the data is shifted out sequentially. it starts from the selected tap location at the most significant bit (511), then wraps around to the least significant bit (0). split register mode in split register mode data can be shifted into or out of one half of the sam, while a split read or split write transfer is being performed on the other half of the sam. conventional (non split) read, or write transfer cycle must precede any split read or split write transfers. the split read and write transfers will not change the sam port mode set by the preceding conventional transfer operation. in the split register mode, serial data can be shifted in or out of one of the split sam registers, starting from any at the 256 tap locations, excluding the last address of each split sam the data is shifted in or out sequentially starting from the selected tap location at the most significant bit (255 or 511) of the first split sam, and then the sam pointer moves to the tap location selected for the second split sam to shift data in or out sequentially, starts from this tap location at the most significant bit (511 or 255), and finally wraps around to the least significant bit. 0 12 255 tap 256 257 511 tap
? semiconductor msm548262 33/37 data transfer operations the msm548262 features two types of bidirectional data transfer capability between ram and sam. 1) conventional (non split) transfer: 512 words by 8 bits of data can be loaded from ram to sam (read transfer), or from sam to ram (write transfer). 2) split transfer: 256 words by 8 bits of data can be loaded from the lower/upper half of the ram to the lower/upper half of the sam (split read transfer), or from the lower/upper half of sam to the lower/upper half of ram (split write transfer). the conventional transfer and split transfer modes are controlled by the dsf input signal. data transfer are invoked by holding the trg signal "low" at the falling edge of ras . the msm548262 supports 4 types of transfer operations: read transfer, split read transfer, write transfer and split write transfer as shown in the truth table. the type of transfer operation is determined by the state of cas , we and dsf latched at the falling edge of ras . during conventional transfer operations, the sam port is switched from input to output mode (read transfer), or output to input mode (write transfer). it remains unchanged during split transfer operation (split read transfer or split write transfer). both ram and sam are divided by the most significant row address (ax8), as shown in figure 1. therefore, no data transfer between ax8 = 0 side ram and ax8 = 1 side ram can be provided through the sam. care must be taken if the split read transfer on ax8 = 1 side (or ax8 = 0 side) is provided after the read transfer or the split read transfer, is provided on ax8 = 0 side (or ax8 = 1 side). figure 1. ram and sam configuration 256 256 8 memory array 256 256 8 memory array 256 256 8 memory array 256 256 8 memory array serial decoder upper sam 256 8 lower sam 256 8 upper sam 256 8 lower sam 256 8 ax8 = 0 ax8 = 1 sam i/o buffer sdq1 - 8
? semiconductor msm548262 34/37 read transfer: ras falling edge --- cas = we = "h", trg = dsf = "l" read transfer consists of loading a selected row of data from the ram into the sam register. a read transfer is invoked by holding cas "high", trg "low", we "high", and dsf "low" at the falling edge of ras . the row address selected at the falling edge of ras determines the ram row to be transferred into the sam. the transfer cycle is completed at the rising edge of trg . when the transfer is completed, the sam port is set into the output mode. in a read/real time read transfer cycle, the transfer of a new row of data is completed at the rising edge of trg , and this data becomes valid on the sdq lines after the specified access time t sca from the rising edge of the subsequent sc cycles. the start address of the serial pointer of the sam is determined by the column address selected at the falling edge of cas . in a read transfer cycle (which is preceded by a write transfer cycle), sc clock must be held at a constant v il or v ih after the sc high time has been satisfied. a rising edge of the sc clock must not occur until after the specified delay t tsd from the rising edge of trg . in a real time read transfer cycle (which is preceded by another read transfer cycle), the previous row data appears on the sqd lines until the trg signal goes "high", and the serial access time t sca for the following serial clock is satisfied. this feature allows for the first bit of the new row of data to appear on the serial output as soon as the last bit of the previous row has been strobed without any timing loss. to make this continuous data flow possible, the rising edge of trg must be synchronized with ras , cas , and the subsequent rising edge of sc (t rth , t cth , and t tsl /t tsd must be satisfied). masked write transfer: ras falling edge --- cas = "h", trg = we = dsf = "l" write transfer cycle consists of loading the content of the sam register into a selected row of the ram. this write transfer is the same as a mask write operation in ram. if the sam data to be transferred must first be loaded through the sam, a masked write transfer operation (all dq pins "low" at falling edge of ras ) must precede the write transfer cycles. a masked write transfer is invoked by holding cas "high", trg "low", we "low" and dsf "low" at the falling edge of ras . the row address selected at the falling edge of ras determines the ram row address into which the data will be transferred. the column address selected at the falling edge of cas determines the start address of the serial pointer of the sam. after the write transfer is completed, the sdq lines are set in the input mode so that serial data synchronized with the sc clock can be loaded. when consecutive write transfer operations are performed, new data must not be written into the serial register until the ras cycle of the preceding write transfer is completed. consequently, the sc clock must be held at a constant v il or v ih during the ras cycle. a rising edge of the sc clock is only allowed after the specified delay t csd from the falling edge of the cas , at which time a new row of data can be written in the serial register. data transferred to sam by read transfer cycle or split read transfer cycle can be written to the other address of ram by write transfer cycle. however, the address to write data must be the same as that of the read transfer cycle (row address ax8).
? semiconductor msm548262 35/37 split data transfer and qsf the msm548262 features a bidirectional split data transfer capability between the ram and sam. during split data transfer operation, the serial register is split into two halves which can be controlled independently. split read or split write transfer operation can be performed to or from one half of the serial register, while serial data can be shifted into or out of the other half of the serial register. the most significant column address location (a8c) is controlled internally to determines which half of the serial register will be reloaded from the ram. qsf is an output which indicates which half of the serial register is in an active state. qsf changes state when the last sc clock is applied to active split sam. split read transfer: ras falling edge --- cas = we = dsf = "h", trg = "l" split read transfer consists of loading 256 words by 8 bits of data from a selected row of the split ram into the corresponding non-active split sam register. serial data can be shifted out from the other half of the split sam register simultaneously. during split read transfer operation, the ram port input clocks do not have to be synchronized with the serial clock sc, thus eliminating timing restrictions as in the case of real time read transfers. a split read transfer can be performed after a delay of t sts from the change of state of the qsf output is satisfied. conventional (non-split) read transfer operation must precede split read transfer cycles. masked split write transfer: ras falling edge --- cas = dsf = "h", trg = we ="l" split write transfer consists of loading 256 words by 8 bits of data from the non-active split sam register into a selected row of the corresponding split ram. serial data can be shifted into the other half of the split sam register simultaneously. during split write transfer operation, the ram port input clocks do not have to be synchronized with the serial clock sc, thus allowing for real time transfer. this write transfer operation, which is the same as a mask write operation in ram, can be selectively controlled for 8 dqis by inputing the mask data from dq1 - dq8 at the falling edge of ras . a split write transfer can be performed after a delay of t sts from the change of state of the qsf output is satisfied. a masked write transfer operation must precede split write transfer. the purpose is to switch the sam port from output mode to input mode, and to set the initial tap location prior to split write transfer operations. power up power must be applied to the ras and trg input signals to pull them "high" before, or at the same time as, the v cc supply is turned on. after power-up, a pause of 200 m s minimum is required with ras and trg held "high". after the pause, a minimum of 8 ras and 8 sc dummy cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer operations can begin. during the initialization period, the trg signal must be held "high". if the internal refresh counter is used, a minimum 8 cas before ras cycles are required instead of 8 ras cycles. (note) initial state after power up the initial state can not be guaranteed for various power up conditions and input signal levels. therefore, it is recommended that the initial state be set after the initialization of the device is performed and before valid operations begin.
? semiconductor msm548262 36/37 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj40-p-400-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.70 typ. mirror finish
? semiconductor msm548262 37/37 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.49 typ. tsop ii 44/40-p-400-0.80-k mirror finish

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